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DS284 june 22, 2011 www.xilinx.com 1 product specification ? copyright 2008-2009, 2011 xilinx, inc. xilinx, the xilinx logo, virtex, spartan, ise and other designated brands included her ein are trademarks of xilinx in the united states and other countries. all other trademarks are the property of their respective owners. introduction the logicore? ip chipscope? pro virtual input/output (vio) core is a customizable core that can both monitor and drive internal fpga signals in real time. two different kinds of inputs and two different kinds of outputs are available, both of which are customizable in size to interface with the fpga design. features ? provides virtual leds and other status indicators through asynchronous and synchronous input ports ? has activity detectors on input ports to detect rising and falling transitions between samples ? provides virtual buttons and other controls through asynchronous and synchronous output ports ? for synchronous outputs, provides ability to define a pulse train, whic h is a 16-cycle train of ones and zeros that run at design speed. logicore ip chipscope pro virtual input/output (vio) (1.04a) DS284 june 22, 2011 product specification logicore ip facts table core specifics supported device family (1) kintex ? -7 (3) , virtex ? -7, virtex-6, virtex-5, virtex-4, spartan ? -6, spartan-3/xa, spartan-3e/xa, spartan-3a/3an/3a dsp/xa supported user interfaces not applicable. provided with core resources frequency configuration (4) luts ffs dsp slices block rams max freq config1 60 87 0 0 399.808 mhz config2 131 291 0 0 399.808 mhz config3 227 543 0 0 399.808 mhz documentation product specification user guide design files netlist example design verilog /vhdl test bench not provided constraints file xilin x constraints file simulation model not provided tested design tools (2) design entry tools core generator tool, xps simulation not provided synthesis tools not provided. support provided by xilinx, inc. notes: 1. for a complete listing of supported derivative devices, see the ids embedded edition derivative device support . 2. for a listing of the supported tool versions, see the ise design suite 13: release note guide . 3. for more information, see ds180 7 series fpgas. 4. overview. for configuration details, see table 6, page 11 .
DS284 june 22, 2011 www.xilinx.com 2 product specification logicore ip chipscope pro virtual input/output (vio) (1.04a) functional description the vio core is a customizable core that can both monitor and drive internal fpga signal s in real time. unlike the ila and iba cores, no on-chip or off-chip ram is required. four types of signals are available in the vio core: ? asynchronous inputs: these are sampled using the jtag clock signal that is dr iven from the jtag cable. the input values are read back periodically and displayed in the analyzer. ? synchronous inputs: these are sampled using the design clock. the input values are read back periodically and displayed in the analyzer. ? asynchronous outputs: these are user-defined in the analyzer and driven out of the core to the surrounding design. a logical 1 or 0 value can be defined for individual asynchronous outputs. ?synchronous outputs: these are user-defined in the analyzer, synchronized to the design clock and driven out of the core to the surrounding design. a logical 1 or 0 can be defined for in dividual synchronous outputs. pulse trains of 16 clock cycles worth of ones and zeros can also be defined for synchronous outputs. activity detectors every vio core input has additional cells to capture the pres ence of transitions on the in put. since the design clock will most likely be much faster than the sample period of the analyzer, it's possible for the signal being monitored to transition many times between succe ssive samples. the activity detectors capture this behavior and the results are displayed along with the value in the analyzer. in the case of a synchronous input, activity cells capable of monitoring for asynchronous and synchronous events are used. this feature can detect glitches as well as synchronous transitions on the synchronous input signal. pulse trains every vio synchronous output has the ability to output a stat ic 1, a static 0, or a puls e train of successive values. a pulse train is a 16-clock cycle sequence of 1s and 0s that drive out of the core on successive design clock cycles. the pulse train sequence is defined in the analyzer and is ex ecuted only one time after it is loaded into the core. x-ref target - figure 1 figure 1: vio core connection to icon core clk control0 control chip s cope pro vio core chip s cope pro icon core a s ync_in a s ync_out s ync_in s ync_out d s 2 8 4_01
DS284 june 22, 2011 www.xilinx.com 3 product specification logicore ip chipscope pro virtual input/output (vio) (1.04a) vio interface ports the i/o signals of the vio core shown in table 1 consist of the control bus to icon, as well as the four interface ports and the design clock. none of the ports are required, but at least one port must be enabled. restrictions a maximum of 15 vio cores can be used in a single design. core generator? the core generator tool provides the ability to define and generate a customized vio core for adding virtual inputs and outputs to your hdl designs. you can customiz e the virtual inputs and outputs to be synchronous to a particular clock in your design or to be completely asynchronous with respect to any clock domain in your design. you can also customize the number of input and output signals used by the vio core. entering the component name the component name field can consist of any combinatio n of alpha-numeric characters in addition to the underscore symbol. however, the underscore symbol ca nnot be the first character in the component name. generating an example design the vio core generator normally generates standard xilinx core generator output files only, such as netlist and instantiation template files. to generate an example de sign that uses the vio core, in addition to the normal generated files, select the generate example design check box. this parameter is stored as example_design in the generated xco parameter file. ta bl e 1 : vio interface ports port name direction description async_in[< m >-1:0] in asynchronous input port of width < m >. optional (depends on enable_asynchronous_input_port). you must declare this port as a vector. for a one-bit port, use async_in[0:0]. async_out[< m >-1:0] out asynchronous output port of width < m >. optional (depends on enable_asynchronous_output_port). this port must be declared as a vector. for a one-bit port, use async_out[0:0]. clk in design clock used to register synchronous in put or output ports. optional (depends on enable_synchronous_input_port and/or enable_synchronous_output_port) control[35:0] inout (1) control bus to icon core. mandatory. sync_in[< m >-1:0] in synchronous input port of width < m >. optional (depends on enable_synchronous_input_port). this port must be declared as a vector. for a one-bit port, use sync_in[0:0]. sync_out[< m >-1:0] out synchronous output port of width < m >. optional (depends on enable_synchronous_output_port). this port must be declared as a vector . for a one-bit port, use sync_out[0:0]. notes: 1. for projects created using xilinx platform studio, the direction for control ports is in.
DS284 june 22, 2011 www.xilinx.com 4 product specification logicore ip chipscope pro virtual input/output (vio) (1.04a) asynchronous input port the vio core includes an asynchronous input port when th e enable asynchronous input port check box is selected. when enabled, you can specify a port width up to 256 bi ts by typing a value in the width text field. the two parameters are stored as enable_asynchronous_input_por t and asynchronous_input_port_width, respectively, in the generated xco parameter file. asynchronous output port the vio core includes an asynchronous output port wh en the enable asynchronous output port check box is selected. when enabled, you can specify a port width up to 256 bits by typing a value in the width text field. the two parameters are stored as enable_asynchronous_output_port and asynchronous_output_port_width, respectively, in the generated xco parameter file. synchronous input port the vio core includes a synchronous input port when the enable synchronous input port check box is selected. when enabled, you can specify a port width up to 256 bi ts by typing a value in the width text field. the two parameters are stored as enable_syn chronous_input_port and synchronous_in put_port_width, respectively, in the generated xco parameter file. synchronous output port the vio core includes a synchronous output port when th e enable synchronous output port check box is selected. when enabled, you can specify a port width up to 256 bi ts by typing a value in the width text field. the two parameters are stored as enable_synchronous_output_po rt and synchronous_output_port_width, respectively, in the generated xco parameter file. inverting the clock edge the vio core can use either a non-inverted or inverted cl k signal to acquire and generate data on the synchronous input and output signals, respectively. the invert clock edge check box is used to invert the clk signal that is coming into the vio core. this parameter is stored as invert_clock_input in the generated xco parameter file. note: the clock can only be inverted if synchronous inputs and/or outputs are used. generating the core after entering the vio core parameters, click generate to create the vio core files. after the vio core has been generated, a list of files that are generated will ap pear in a separate window called "readme ".
DS284 june 22, 2011 www.xilinx.com 5 product specification logicore ip chipscope pro virtual input/output (vio) (1.04a) using the vio core to instantiate the example vio core hdl files into your design, use the following guidelines to connect the vio core port signals to various signals in your design: ? connect the vio core's control port signal to an un used control port of the icon core instance in the design ? connect all unused bits of the vio core's asynchronous and synchronous input signals to a "0". this prevents the mapper from removing the unused trigger and/or data signals and also avoids any drc errors during the implementation process ? for best results, make sure the synchronous input so urce signals are synchronous to the vio clock signal (clk); also make sure the synchronous output sink signals are synchronous to the vio clock signal (clk) example 1: vio connection in vhdl and show how the vio core is connected in vhdl and verilog respectively. note how the control bus control0 is attached to the co ntrol port of the vio. in the verilog example an empty module declaration is created for the icon and vio module . this is used as a black box declaration so that the synthesis tool properly accoun ts for the generated netlists. example 1: vio connection in vhdl entity example_chipscope_vio is port ( clk_i : in std_logic ); end example_chipscope_icon; architecture vio_arch of example_chipscope_vio is --------------------------------------------------------------------- -- -- component declarations -- --------------------------------------------------------------------- component chipscope_icon port ( control0 : inout std_logic_vector(35 downto 0)); end component; component chipscope_vio port ( control ?? : inout std_logic_vector(35 downto 0); clk ?? : in std_logic; async_in ?? : in std_logic_vector(7 downto 0); async_out ?? : out std_logic_vector(7 downto 0); sync_in ?? std_logic_vector(7 downto 0); sync_out ?? out std_logic_vector(7 downto 0) ); end component; ------------------------------------------------------------------- -- local signals ------------------------------------------------------------------- signal control_0 ?? :std_logic_vector (35 downto 0); signal async_i ?? :std_logic_vector (7 downto 0); signal async_o ?? :std_logic_vector (7 downto 0); signal sync_i ?? :std_logic_vector (7 downto 0); signal sync_o ?? :std_logic_vector (7 downto 0); -------------------------------------------------------------------
DS284 june 22, 2011 www.xilinx.com 6 product specification logicore ip chipscope pro virtual input/output (vio) (1.04a) -- -- icon pro core instance -- ------------------------------------------------------------------- icon_inst: chipscope_icon port map ( control0 => control0); ------------------------------------------------------------------- -- -- vio pro core instance -- ------------------------------------------------------------------- vio_inst : chipscope_vio port map ( control ?? => control_0, clk ?? => clk_i, async_in ?? => async_i, async_out ?? => async_o, sync_in ?? => sync_i, sync_out ?? => sync_o ); example 2: vio connection in verilog module example_chipscope_vio ( input clk_i ); //----------------------------------------------------------------- // local signals //----------------------------------------------------------------- wire [35:0] control_0; wire [7:0] async_i; wire [7:0] async_o wire [7:0] sync_i; wire [7:0] sync_o; //----------------------------------------------------------------- // // icon pro core instance // //----------------------------------------------------------------- chipscope_icon icon_inst ( .control0(control0)); //----------------------------------------------------------------- // // vio pro core instance // //----------------------------------------------------------------- chipscope_vio vio_inst0 ( .control(control0), .clk(clk_i), .async_in(async_i), .async_out(async_o), .sync_in(sync_i),
DS284 june 22, 2011 www.xilinx.com 7 product specification logicore ip chipscope pro virtual input/output (vio) (1.04a) .sync_out(sync_o)); endmodule //------------------------------------------------------------------- // // icon pro core module declaration // //------------------------------------------------------------------- module chipscope_icon ( inout [35:0] control0); endmodule //------------------------------------------------------------------- // // vio pro core module declaration // //------------------------------------------------------------------- module chipscope_vio ( inout [35:0] control, input [7:0] async_in, output [7:0] async_out, input [7:0] sync_in, output [7:0] sync_out); endmodule xilinx platform studio using the vio core in the em bedded development kit (edk) the vio core can be inserted into an embedded processor design using the edk. in this case, the vio core depends on icon and opb_mdm component instances already being in the design, as shown in figure 2 . x-ref target - figure 2 figure 2: vio core connection to icon core clk control chip s cope pro vio core a s ync_in a s ync_out s ync_in s ync_out control0 chip s cope pro icon core capture_in tdi_in re s et_in s hift_in update_in s el_in drck_in tdo_ out mdm capture_in tdi_in re s et_in s hift_in update_in s el_in drck_in tdo_ out d s 2 8 4_02
DS284 june 22, 2011 www.xilinx.com 8 product specification logicore ip chipscope pro virtual input/output (vio) (1.04a) in edk, the vio core is integrated into the tool usin g a tcl script. when the edk hardware platform generator (platgen) tool is run, the tcl script is called and the script internally calls core generator? in command line mode. the tcl script provides the core generator an arguments file (.xco) to generate the vio core netlist. the tcl script also generates an hdl wrapper to match the vio ports based on the core parameters found in ta ble 2 . the xilinx synthesis technology (xst) tool is used to sy nthesize the wrapper hdl generated for the vio core. the ngc netlist outputs from the xst tool and the chipscope pro core generator are subsequently incorporated into the xilinx ise tool suite for actual device implementation. ta bl e 2 : edk-specific parameters parameter name allowable values default value description c_async_input_enable 0, 1 0 0 = disable port, 1 = enable port c_async_input_width 1-256 8 asynchronous input port width, if used c_async_output_enable 0, 1 0 0 = disable port, 1 = enable port c_async_output_width 1-256 8 asynchronous output port width, if used c_family virtex4, virtex 5, virtex6, virtex6l, virtex7, kintex7, spartan3, spartan3a, spartan3adsp, spartan3e, spartan6, spartan6l, aspartan3, aspartan3a, aspartan3adsp, aspartan3e, aspartan6, avirtex4, qspartan6, qspartan6l, qrvirtex4, qspartan6, qspartan6l, qvirtex4, qvirtex5, qvirtex6 n/a device family to use. c_rising_clock_edge 0, 1 1 edge of input clock to use. 0 = falling edge, 1 = rising edge c_sync_input_enable 0, 1 0 0 = disable port, 1 = enable port c_sync_input_width 1-256 8 synchronous input port width, if used c_sync_output_enable 0, 1 0 0 = disable port, 1 = enable port c_sync_output_width 1-256 8 synchronous output port width, if used c_use_srl16s 0, 1 1 0 = do no use srl16s, 1 = use srl16s
DS284 june 22, 2011 www.xilinx.com 9 product specification logicore ip chipscope pro virtual input/output (vio) (1.04a) ports and parameters ports vio interface ports the i/o signals of the vio core shown in table 3 consist of the control bus to icon, as well as the four interface ports and the design clock. none of the ports are required, but at least one port must be enabled. ta bl e 3 : vio interface ports port name direction description async_in[< m >-1:0] in asynchronous input port of width < m >. optional (depends on enable_asynchronous_input_port). you must declare this port as a vector. for a one-bit port, use async_in[0:0]. async_out[< m >-1:0] out asynchronous output port of width < m >. optional (depends on enable_asynchronous_output_port). this port must be declared as a vector. for a one-bit port, use async_out[0:0]. clk in design clock used to register synchronous in put or output ports. optional (depends on enable_synchronous_input_port and/or enable_synchronous_output_port) control[35:0] inout (1) control bus to icon core. mandatory. sync_in[< m >-1:0] in synchronous input port of width < m >. optional (depends on enable_synchronous_input_port). this port must be declared as a vector. for a one-bit port, use sync_in[0:0]. sync_out[< m >-1:0] out synchronous output port of width < m >. optional (depends on enable_synchronous_output_port). this port must be declared as a vector . for a one-bit port, use sync_out[0:0]. notes: 1. for projects created using xilinx platform sturdio, the direction for control ports is in.
DS284 june 22, 2011 www.xilinx.com 10 product specification logicore ip chipscope pro virtual input/output (vio) (1.04a) parameters core generator parameters xco parameters xps parameters ta bl e 4 : xco parameters parameter name allowable values default value description component_name string with a-z, 0-9, and _ (underscore) vio name of instantiated component enable_asynchronous_input_port true, false false enables the async_in port enable_asynchronous_output_port true, false false enables the async_out port enable_synchronous_input_port true, false false enables the sync_in port enable_synchronous_output_port true, false false enables the sync_out port asynchronous_input_port_width 1-256 8 width of the async_in port asynchronous_output_port_width 1-256 8 width of the async_out port synchronous_input_port_width 1-256 8 width of the sync_in port synchronous_output_port_width 1-256 8 width of the sync_out port invert_clock_input true, false false invert the design clock input example_design false = do not generate sample, true = generate example false enable generration of an example design for the core. ta bl e 5 : edk-specific parameters parameter name allowable values default value description c_async_input_enable 0, 1 0 0 = disable port, 1 = enable port c_async_input_width 1-256 8 asynchronous input port width, if used c_async_output_enable 0, 1 0 0 = disable port, 1 = enable port c_async_output_width 1-256 8 asynchronous output port width, if used c_family virtex4, virtex 5, virtex6, virtex6l, virtex7, kintex7, spartan3, spartan3a, spartan3adsp, spartan3e, spartan6, spartan6l, aspartan3, aspartan3a, aspartan3adsp, aspartan3e, aspartan6, avirtex4, qspartan6, qspartan6l, qrvirtex4, qspartan6, qspartan6l, qvirtex4, qvirtex5, qvirtex6 n/a device family to use. c_rising_clock_edge 0, 1 1 edge of input clock to use. 0 = falling edge, 1 = rising edge c_sync_input_enable 0, 1 0 0 = disable port, 1 = enable port c_sync_input_width 1-256 8 synchronous input port width, if used c_sync_output_enable 0, 1 0 0 = disable port, 1 = enable port c_sync_output_width 1-256 8 synchronous output port width, if used c_use_srl16s 0, 1 1 0 = do no use srl16s, 1 = use srl16s
DS284 june 22, 2011 www.xilinx.com 11 product specification logicore ip chipscope pro virtual input/output (vio) (1.04a) performance and resource utilization the performance and utiliztion data is shown in table 6 . verification xilinx has verified the vio core in a proprietary test environment, using an intern ally developed bus functional model. references 1. more information on the chipscope pro software and core s is available in the software and cores user guide, located at http://www.xilinx.com/documentation . 2. information about hardware debugging using chipscope pr o in edk is available in the platform studio online help, located at http://www.xilinx.com/documentation . information about hardware debugging using chipscope pro in system generator for dsp is available in the xilinx system generator for dsp user guide, located at http://www.xilinx.com/documentation . support xilinx provides technical support for this logicore product when used as described in the product documentation. xilinx cannot guarantee timing, functionality, or support of product if implemented in devices that are not defined in the documentation, if customized be yond that allowed in the product documentation, or if changes are made to any section of the design labeled do not modify. ordering information this xilinx logicore ip module is provided at no additional cost with the xilinx ise ? design suite embedded edition software under the terms of the xilinx end user license . the core is generated using the xilinx ise design suite software. for more information, visit the chipscope vio page. information about this and other xilinx lo gicore ip modules is available at the xilinx intellectual property page. for information on pricing and availability of other xilinx logicore modules and software, please contact your local xilinx sales representative . ta bl e 6 : performance and utilization for specific configuration details configuration name device vio setup config1 xc5vlx20t-2ff323 asynchonous input port (7:0) config2 xc5vlx20t-2ff323 asynchonous input port (7:0), synchronous input port (7:0), asynchonous output port (7:0), synchonous output port (7:0) config3 xc5vlx20t-2ff323 asynchonous input port (15:0), synchronous input port (15:0), asynchonous output port (15:0), synchonous output port (15:0)
DS284 june 22, 2011 www.xilinx.com 12 product specification logicore ip chipscope pro virtual input/output (vio) (1.04a) revision history notice of disclaimer xilinx is providing this product documentation, hereinafter ?inf ormation,? to you ?as is? with no warranty of any kind, express or implied. xilinx makes no representation that the information, or any particular implementation thereof, is free from any claims of infringement. you are responsible for obtaining any rights you may require for any implementation based on the information. all specifications are subject to change without notice. xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the information or any implementation based thereon, including but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose. ex cept as stated herein, none of the information may be copied, reproduced, distributed, republished, downloaded, displ ayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or ot herwise, without the prior written consent of xilinx. date version description of revisions 03/24/08 1.0 release 10.1 (initial xilinx release). 09/19/08 2.0 release 10.1, service pack 3. 04/07/09 3.0 release 11.1. 06/24/09 3.1 release 11.2. 09/16/09 3.1.1 corrections to document. pu blished with 11.3 software release. 6/22/11 3.2 updated to v1.04a for the 13.2 release.

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